THine Value Extending MIPI Transmission with V-by-One HS: Simplifying SerDes Chipset Selection for Embedded Cameras (Main-Link Part)
2022.08.15
- Article
- Use Case
A world full of cameras—it's no longer science fiction. Today, cameras are found not only in smartphones, tablets, laptops, and digital and surveillance cameras but also in cars, industrial machines, medical and educational equipment, IoT devices, factory inspection systems, and even drones.
As cameras become standard across such a wide range of devices, it's natural that electronics manufacturers have increasingly diverse requirements. One such demand is the long-distance transmission of video signals. MIPI® CSI-2 signals output from a camera module are typically limited to 20–30 centimeters in transmission distance. However, in many applications—such as industrial robots or agricultural IoT systems—the camera module and host processor (SoC) cannot be installed close together.
A promising solution for such cases is the high-speed interface technology V-by-One® HS. By converting MIPI CSI-2 signals into V-by-One HS signals, the transmission range can be extended up to 15 meters. This transmission range meets the need for long-distance delivery of captured video signals, a key requirement for many electronics manufacturers.
However, choosing the optimal SerDes chipset (transmitter and receiver ICs) for systems that extend MIPI CSI-2 transmission using V-by-One HS is no easy task. Reviewing datasheets, evaluating various parameters, and estimating settings for the best-fit SerDes chipset often requires a considerable investment of time and effort.
As cameras become standard across such a wide range of devices, it's natural that electronics manufacturers have increasingly diverse requirements. One such demand is the long-distance transmission of video signals. MIPI® CSI-2 signals output from a camera module are typically limited to 20–30 centimeters in transmission distance. However, in many applications—such as industrial robots or agricultural IoT systems—the camera module and host processor (SoC) cannot be installed close together.
A promising solution for such cases is the high-speed interface technology V-by-One® HS. By converting MIPI CSI-2 signals into V-by-One HS signals, the transmission range can be extended up to 15 meters. This transmission range meets the need for long-distance delivery of captured video signals, a key requirement for many electronics manufacturers.
However, choosing the optimal SerDes chipset (transmitter and receiver ICs) for systems that extend MIPI CSI-2 transmission using V-by-One HS is no easy task. Reviewing datasheets, evaluating various parameters, and estimating settings for the best-fit SerDes chipset often requires a considerable investment of time and effort.
Main-Link: Verifying Data Rate Requirements
To reduce the time and effort required to select the right camera SerDes, we have prepared support documents to streamline the process. One is a design guide for the Main-Link that handles image signal transmission. The other is a Sub-Link design guide for control signal transmission (to be released separately). These two design guides make it easier to select the optimal V-by-One HS transmitter and receiver ICs.
Let us start with the Main-Link design guide. Typically, electronics manufacturers select the camera module and SoC for their application at an early stage of development. As a result, key specs such as resolution, frame rate (refresh rate), color depth, and interface standards are usually defined early on. Based on these specs, manufacturers can then choose appropriate V-by-One HS transmitter and receiver ICs (see Figs. 1 and 2).
Transmitter IC options include THCV241A, THCV241A-P, THCV243, and THCV231. Receiver IC options include THCV242A, THCV242A-P, THCV244A, THCV244A-QP, and THCV236.
However, a key consideration is whether the combined transmitter and receiver ICs can support the required data rate. In some cases, the data lanes of both MIPI CSI-2 and V-by-One HS may not meet the application's bandwidth requirements. Specifically, MIPI CSI-2 supports 0.08 G to 1.5 Gbps, while V-by-One HS supports 0.400 G to 4.0 Gbps. Transmission must fall within these ranges.
The design guide includes a simple way to verify whether your chosen transmitter and receiver pair meet the necessary data rate requirements (see Fig. 3).
In the table, gray cells indicate data rates outside the supported range for either MIPI CSI-2 or V-by-One HS, meaning the IC pair cannot support those scenarios. Yellow cells show configurations where THCV241A and THCV242A are insufficient, but the higher-speed THCV241A-P and THCV242A-P combination is valid. This is because the THCV241A-P and THCV242A-P support up to 1.5 Gbps per MIPI CSI-2 lane, compared to 1.2 Gbps for THCV241A and THCV242A.
These data rate checks can also be performed manually using the "Target Pixel Clock" formulas provided in the datasheets. However, the manual method requires collecting and calculating multiple parameters, which can be time-consuming. The new design guide eliminates the need for manual calculation, allowing for quicker and more efficient validation.
Let us start with the Main-Link design guide. Typically, electronics manufacturers select the camera module and SoC for their application at an early stage of development. As a result, key specs such as resolution, frame rate (refresh rate), color depth, and interface standards are usually defined early on. Based on these specs, manufacturers can then choose appropriate V-by-One HS transmitter and receiver ICs (see Figs. 1 and 2).
Fig. 1 Configuration example with one camera module
Fig. 2 Configuration example with four camera modules
Transmitter IC options include THCV241A, THCV241A-P, THCV243, and THCV231. Receiver IC options include THCV242A, THCV242A-P, THCV244A, THCV244A-QP, and THCV236.
However, a key consideration is whether the combined transmitter and receiver ICs can support the required data rate. In some cases, the data lanes of both MIPI CSI-2 and V-by-One HS may not meet the application's bandwidth requirements. Specifically, MIPI CSI-2 supports 0.08 G to 1.5 Gbps, while V-by-One HS supports 0.400 G to 4.0 Gbps. Transmission must fall within these ranges.
The design guide includes a simple way to verify whether your chosen transmitter and receiver pair meet the necessary data rate requirements (see Fig. 3).
Fig. 3 Data rate check table
In the table, gray cells indicate data rates outside the supported range for either MIPI CSI-2 or V-by-One HS, meaning the IC pair cannot support those scenarios. Yellow cells show configurations where THCV241A and THCV242A are insufficient, but the higher-speed THCV241A-P and THCV242A-P combination is valid. This is because the THCV241A-P and THCV242A-P support up to 1.5 Gbps per MIPI CSI-2 lane, compared to 1.2 Gbps for THCV241A and THCV242A.
These data rate checks can also be performed manually using the "Target Pixel Clock" formulas provided in the datasheets. However, the manual method requires collecting and calculating multiple parameters, which can be time-consuming. The new design guide eliminates the need for manual calculation, allowing for quicker and more efficient validation.