THine has developed All-Digital Burst-Mode CDR that achieves the fastest-level data link recovery time and extremely low stand-by power consumption through a joint research with the University of Tokyo
Tokyo (September 25, 2013) – THine Electronics, Inc. (JASDAQ: 6769), the global leader in high-speed serial interface and provider of mixed-signal LSI, today announced its development of all-digital burst-mode clock-data-recovery (CDR) technology that achieves the world fastest-level data link recovery time and extremely low stand-by power consumption through a joint research with the University of Tokyo. THine and the University of Tokyo make a presentation on this achievement at The IEEE Custom Integrated Circuits Conference (CICC) held from September 23rd at San Jose, California, U.S.A.
Recent spread of mobile consumer electronics has rapidly increased amount of data handled by digital devices. On the other hand, reduction in their power consumption and circuit area is required more than ever since digital equipments have constraints in lasting-hour of batteries and limited internal space to achieve their electronic systems.
Data communication of mobile device, for instance in touch panel operation, has switching behavior of data transmission that consists of burst-mode and stand-by mode. So mobile applications significantly require not only low power consumption and high-speed performance in operation, but also low stand-by power consumption and fast data link recovery time.
In order to solve these constraints, THine, collaborating with the University of Tokyo, conducted joint research and has developed basic circuit technology that can drastically reduce power consumption and circuit area for digital devices with burst-mode.
THine has achieved the breakthrough using all-digital circuits in order to overcome the assumed limitation of analog circuit technology in the future since the recent LSI manufacturing process generally uses as low level voltage as 1 V.
THine’s achievement with the University of Tokyo includes reference-less all-digital burst-mode CDR, reducing costs and circuit occupation area, and has three features as follows:
(1) the proposed burst-mode CDR circuit realizes true 4-cycle lock without any warm-up operations after power-
on in frequency range from 1.40 to 2.06 Gb/s,
(2) the new architecture utilizes a phase generator with embedded time-to-digital converter (TDC) to detect
a frequency and to recover a correct clock phase, while general CDR requires additional TDC, and
(3) the developed circuits suppress increase of circuit area by the coarse-fine hierarchical architecture of TDC
while wide-range bandwidth operations are available.
In this joint research activity, THine has led the technical concept and developed evaluation and application technology while the University of Tokyo has led major technical breakthroughs to achieve essential key technologies. Professor Kunihiro Asada, Assistant Professor Tetsuya Iizuka, and their research team of the Department of Electrical Engineering and Information Systems, the University of Tokyo achieved the features above and the extraordinarily small circuit in a 65 nm CMOS with 80 x 80 µm2 area.
A chip micrograph and a layout of the proposed CDR
The achievement, potentially, can be applied to broad application markets with burst-mode in high-speed data communication, for instance, mobile devices, sensor network usages, and industrial equipments with time-sharing reciprocal data communication. Many future applications are expected to have their solution in lower power consumption, higher-speed, smaller footprints, and long lasting battery operations by adopting these achievements.
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