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THine has developed fast-lock all-digital CDR that achieves significant jitter tolerance through a joint research with the University of Tokyo


2016/09/15

Tokyo (September 15, 2016) – THine Electronics, Inc. (JASDAQ: 6769), the global leader in high-speed serial interface and provider of mixed-signal LSI, today announced its development of fast-lock all-digital clock-data-recovery (CDR) technology that achieves significant jitter tolerance by newly developed frequency following techniques, in addition to fast-lock feature and extremely low power in the stand-by mode, through a joint research with the University of Tokyo. The University of Tokyo and THine made a presentation on this achievement at the IEEE’s European Solid-State Circuits Conference, held from September 12th, 2016 at Lausanne, Switzerland.
 
1. Background of the Research and Development and its Target
Recent spread of Internet of Everything and big data utilization has rapidly increased amount of data handled by digital devices or cloud network servers. Such trends make data transmission speed and power consumption significantly important among system features. Especially because of constraints in power consumption conditions of digital devises, as much reduction of power consumption as possible is required more than ever.
THine, collaborating with the University of Tokyo through the joint research, developed all-digital CDR technology for digital devises with burst-mode signals, achieving extremely low power consumption and excellent recovery time. In addition to such previous features, THine and the University of Tokyo has achieved the significant noise tolerance that contributes to faster data transmission in a normal mode.
 
2. Achievement through the joint research
THine’s achievement with the University of Tokyo includes fast-lock reference-less all-digital burst-mode CDR with significant jitter tolerance by new techniques in starting the phase-locked loop operation. The new frequency following architecture combined of a coarse digitally controllable delay line (DCDL) and a fine DCDL with a digital phase detector and a digital controller enables recovered clock to be a wide range and a fine resolution by detecting errors and adjusting the delay time dynamically. The newly developed fractional phase selection technique achieves significant jitter tolerance, wide frequency range, and precise frequency resolution as follows:
(1) the proposed burst-mode CDR circuit realizes true 4-cycle lock without any warm-up operations after power-on in wide frequency range from 1.2 to 2.3 Gbps (giga bit per second),
(2) the new CDR achieves extremely low power consumption in stand-by mode and consumes such a low power of 13.2 ~ 24.6 mW in operating state, and
(3) the developed circuits achieved significant jitter tolerance with approximately 20 times longer tolerance in consecutive identical digits (CID) than the previously developed circuits.
 
This joint research activity has been conducted by THine and the research team of the University of Tokyo, including Professor Kunihiro Asada, Associate Professor Toru Nakura, and Associate Professor Tetsuya Iizuka.



The circuit block diagram and photo of the fast-lock all-digital CDR with significant jitter tolerance by THine and the University of Tokyo



3. Potential applications
The expansion of IoE leads wider application of sensor networks, AR (augmented reality) / VR (virtual reality) systems, and autonomous driving systems / ADAS (advanced driving assistance systems). This newly developed technology potentially can be applied to these applications in highly-precise operation of burst-mode state that require low power consumption, higher-speed, smaller fingerprints, and higher jitter tolerance.

 
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