THine's well proven LVDS interface IP core can be utilized for ASIC with built in Timing Controller or User Logic, integrating all necessary function into 1 chip. 1 chip solution eliminates the trouble of EMI around the circuit as well as reduction of cost, space and Power consumption. Utilizing high speed interface such as RSDS/mini-LVDS for output port controller chips for QXGA and QSXGA can be integrated into 1 chip.

■Supports LVDS Single/Dual Pixel Data Transmission
■Supports 6bit/8bit/10bit
■Hi FRC available
■User defined Logic for Control Signal available
■Lower EMI
■Lower Power
■Wide Frequency Range 25~160MHz (LVDS)
■Power Supply Single 3.3V/2.5V or 3.3/2.5V ,3.3/1.8V, 3.3/1.2V, 3.3/1.0V mixed available
■0.35um/0.25um/0.18um/0.13um/90nm CMOS process
■Power Down mode
■QFP/TQFP/LQFP/QFN/BGA available